Senior Design Engineer @ VerveSemi • PhD @ IIT Roorkee
Amandeep Singh
Senior Research Fellow @ IIT Roorkee
Ph.D. in Electronics & Communication Engineering (VLSI & IMC)
Senior Research Fellow @ IIT Roorkee
Ph.D. in Electronics & Communication Engineering (VLSI & IMC)
Pioneering energy-efficient In-Memory Computing architectures, custom SRAM macros, and silicon-proven hardware acceleration for edge AI applications.
PhD Researcher @ IIT Roorkee
Working in the digital design team at VerveSemi Microelectronics, contributing to the architectural design, logic synthesis, static timing analysis, and physical implementation of cutting-edge semiconductor IPs and SoC solutions.
TSMC 65nm Foundry Silicon
VLSID 2025 & 2026 • Consecutive Wins
Complete Industry Design Flows
Prestigious National & Global Honors
Specializing in In-Memory Computing architectures for energy-efficient AI acceleration. My research bridges the gap between custom circuit design and system-level AI applications through silicon-proven innovations.
Industry execution in digital ASIC flow, protocol design, synthesis, and physical implementation.
Senior Design Engineer
Driving the complete digital design cycle from RTL coding through post-layout verification. My core responsibilities include architectural specification, microarchitecture design, logic synthesis, static timing analysis (STA), clock domain crossing (CDC) checks, and physical design mapping to achieve ultra-tight PPA (Power, Performance, Area) targets for high-reliability semiconductor IPs.
Architected and implemented a robust Serial Peripheral Interface (SPI) IP core covering the entire VLSI design flow from RTL specification to signed-off GDSII post-layout simulation:
Industry-proven proficiency across hardware description, electronic design automation, and IC testing.
RTL modeling, simulation scripting, and algorithmic verification
Industry standard Cadence, Synopsys, and Xilinx toolchains
Specialized circuit architectures and physical design methodologies
TSMC 65nm CMOS • 2mm × 2mm
A robust and PVT-insensitive Time-Domain In-Memory Compute architecture using an SRAM array, designed to adaptively compensate and control process, voltage, and temperature variations.
TSMC 65nm CMOS • 1.53mm × 1.5mm
Integrates custom Voltage-Controlled Delay Cells (VCDC) with a dense SRAM array to execute highly parallel XAC and MAC arithmetic operations for edge AI vision workloads.
TSMC 65nm CMOS • 1mm × 1.09mm
A high-throughput in-memory crypto architecture designed to accelerate Secure Hash Algorithm-3 (SHA-3), implementing parallel 5-input XOR and fused XOR-Rotation operations in memory.
IC Testing Laboratory, IIT Roorkee
Custom high-frequency testbench and PCB validation platform for silicon verification, clock characterization, and power profiling of fabricated ICs.
Rigorous academic foundation in Electronics Engineering and VLSI System Design.
Indian Institute of Technology, Roorkee
Specialization: In-Memory Computing & VLSI Circuit Design
Punjab Engineering College (PEC), Chandigarh
Specialization: VLSI Circuit Design
Guru Gobind Singh College, Kharar
Electronics and Communication Engineering
Central Public School, Ghoman
Non-Medical Sciences & Mathematics
S.G.H.K. Public School, Ghoman
General Science & Secondary Education
In-depth research projects spanning AI accelerators, crypto engines, and mixed-signal blocks.
XAC & Multibit MAC Operations
Binary Neural Networks (BNN)
In-Memory Security & Keccak IP
128×128 6T-SRAM Array
LED Strip & Persistence of Vision
Analog Circuit Design
Low-Power High-Speed Comparison
C-DAC Mohali
Peer-reviewed research contributions in premier IEEE journals and flagship conferences.
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad
IEEE Transactions on Nanotechnology (TNANO), 2023
IEEE Transactions on Nanotechnology (TNANO)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
National design awards, international travel grants, and academic fellowships.
Pune, Maharashtra
Won the Digital Tape-Out Winner medal at the 39th VLSI & 25th Embedded Conference for: "A Configurable Time-Domain In-Memory Computing Macro for Multi-Bit MAC and Binary XAC Operations in Edge AI Devices". Awarded a prize cheque of ₹50,000.
Pune, Maharashtra
Selected for the prestigious VLSID 2026 Fellowship under the Tapeout category based on distinguished research contributions in digital circuit design.
Pune, Maharashtra
Presented winning research on configurable TD-IMC macros at the official Award Ceremony of the 39th International VLSI Design Conference.
Prize Cheque ₹50,000
Received the Best Design Tapeout Award – Digital category, including an honorary prize cheque of ₹50,000 at VLSID 2026.
Bengaluru, Karnataka
Honored with the Best Digital IC Tapeout Award at the 38th International Conference on VLSI Design as part of the IIT Roorkee chip design team.
Bengaluru, Karnataka
Received official certificate for the Best Digital IC Tapeout Award, recognizing outstanding contribution in digital IC tapeout design at VLSID 2025.
Bengaluru, Karnataka
Selected as a Student Fellow (SFN417) with full conference registration sponsorship, accommodation, and travel grant support.
ISCAS 2024, Singapore
Awarded by the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Govt. of India to present research at IEEE ISCAS 2024.
ISCAS 2024, Singapore
Recipient of the prestigious 2024 IEEE Circuits and Systems Society (CASS) Student Travel Grant for presenting research in Singapore.
Kolkata, West Bengal
Selected as a Fellow (SF104) from over 600 nationwide applicants for the 37th International Conference on VLSI Design.
Score: 645 | Marks: 52.67
Secured All India Rank 1517 in Electronics and Communication Engineering among over 100,000 engineering candidates nationwide.
Score: 446 | Marks: 37.00
Secured All India Rank 4438 in Electronics and Communication Engineering qualification.
Score: 598 | Marks: 47.07
Secured All India Rank 2667 in Electronics and Communication Engineering qualification.
Visual highlights from conference stages, awards, video interviews, and testing laboratories.
Pune • 39th VLSI Design Conference
Honored with the Best Digital IC Tapeout Award at VLSID 2026, marking a consecutive second-time triumph in digital tapeouts.
Pune • 39th VLSI Design Conference
Live stage recording during the grand Award Ceremony of VLSID 2026, receiving the Best Digital IC Tapeout Trophy.
Pune, India
Commemorating participation and paper presentations at the 39th International Conference on VLSI Design.
with Rajat Kumar Singh, Founder & CEO
Featured technical interview discussing critical EDA tools, silicon flows, and methodologies required for tapeouts and post-silicon testing.
Pune, India
Presenting measured chip test results and silicon validation of the fabricated Time-Domain IMC macro to conference delegates.
Singapore EXPO Convention
Presenting "PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks" at IEEE ISCAS 2024.
IIT Roorkee
The laboratory where 3 silicon tapeouts were architected, laid out, and functionally tested under Prof. Bishnu Prasad Das.
Fellow (SFO1041)
Certificate of Participation for attending the 39th International Conference on VLSI Design as an invited Fellow.
Tapeout Selection
Certificate for the presented tapeout research on Time-Domain IMC architectures at VLSID 2026.
Singapore
Certificate of attendance and presentation at the IEEE International Symposium on Circuits and Systems (ISCAS).
Kolkata, India
Attended as an honored VLSID 2024 Fellow at the 37th International VLSI Design Conference.
Ahmedabad, India
Presented paper on "Area-Efficient In-Memory Computation" at the 9th International Symposium on Smart Electronic Systems.
Virtual Event
Fellowship Certificate for contribution and research participation at the 34th International Conference on VLSI Design.
Mohali, Punjab
Completed industrial training on "Design and Development of Embedded-Based Quiz Systems" using 8051 architectures.
Digital System Design
Recognized for contributions as teaching staff in digital system design online courses with Prof. Bishnu Prasad Das.
VLSI Physical Design
Certificate of Appreciation for transcribing and curating course lectures for NPTEL VLSI Physical Design courses.
Feel free to reach out with any academic inquiries, research queries, or general questions.
Feel free to reach out directly through any of the channels below:
Dr. Bishnu Prasad Das
Professor, Department of Electronics and Communication Engineering
Indian Institute of Technology (IIT) Roorkee
Have a question regarding my VLSI research, publications, or tapeout projects? Feel free to send your query.
Please provide your professional details below to request Amandeep's latest Silicon Design & VLSI Research CV.